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vishay siliconix si6924aedq document number: 72215 s-81056-rev. b, 12-may-08 www.vishay.com 1 n-channel 2.5-v (g-s) battery switch, esd protection features ? halogen-free ? low r ds(on) ?v gs max rating: 14 v ? exceeds 2 kv esd protection ? 28 v v ds rated ? symmetrical voltage blocking (off voltage) product summary v ds (v) r ds(on) ( )i d (a) 28 0.033 at v gs = 4.5 v 4.6 0.038 at v gs = 3.0 v 4.3 0.042 at v gs = 2.5 v 4.1 description the si6924aedq is a dual n-channel mosfet with esd protection and gate over-vol tage protection circuitry incorporated into the mosfet. the device is designed for use in lithium ion battery pack circuits. the common-drain construction takes advantage of the typical battery pack topology, allowing a further reduction of the device?s on- resistance. the 2-stage input protection circuit is a unique design, consisting of two stages of back-to-back zener diodes separated by a resistor. the first stage diode is designed to absorb most of the esd energy. the second stage diode is designed to protect the gate from any remaining esd energy and over-voltages above the gates inherent safe operating range. the series resistor used to limit the current through the se cond stage diode during over voltage conditions has a maximum value which limits the input current to 10 ma at 14 v and the maximum t off to 12 s. the si6924aedq has been optimized as a battery or load switch in lithium ion applications with the advantage of both a 2.5 v r ds(on) rating and a safe 14 v gate-to-source maximum rating. application circuits figure 1. typical use in a lithium ion battery pack battery protection circuit esd and overvoltage protection esd and overvoltage protection *thermal connection to drain p ins is re q uired to achieve s p ecific p erformance figure 2. input esd and overvoltage protection circuit g r** s d **r typical value is 3.3 k by design. see typical characteristics, gate-current vs. gate-source v oltage, page 3. rohs compliant
www.vishay.com 2 document number: 72215 s-81056-rev. b, 12-may-08 vishay siliconix si6924aedq functional block diagram and pin configuration notes: a. surface mounted on fr4 board. figure 3. ordering information: SI6924AEDQ-T1-GE3 (lead (pb)-free and halogen-free) si6924aedq d s 1 s 1 g 1 1 2 3 4 8 7 6 5 d s 2 s 2 g 2 tssop-8 top view figure 4. g 1 s 1 g 2 s 2 n-channel n-channel 3.3 k 3.3 k *d *d *thermal connection to drain pins is required to achieve specific performance . absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 10 s steady state unit drain-source voltage, source-drain voltage v ds 28 v gate-source voltage v gs 14 continuous drain-to-source current (t j = 150 c) a t a = 25 c i d 4.6 4.1 a t a = 70 c 3.7 3.2 pulsed drain-to-source current i dm 20 pulsed source current (diode conduction) a i s 1.2 0.9 maximum power dissipation a t a = 25 c p d 1.3 1.0 w t a = 70 c 0.84 0.64 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 10 s r thja 71 95 c/w steady state 96 125 maximum junction-to-foot (drain) steady state r thjf 56 70
document number: 72215 s-81056-rev. b, 12-may-08 www.vishay.com 3 vishay siliconix si6924aedq notes: a. guaranteed by design, not subject to production testing. b. pulse test; pulse width 300 s, duty cycle 2 %. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.6 1.5 v gate-body leakage i gss v ds = 0 v, v gs = 4.5 v 1 a v ds = 0 v, v gs = 14 v 20 ma zero gate voltage drain current i dss v ds = 22.4 v, v gs = 0 v 1 a v ds = 22.4 v, v gs = 0 v, t j = 55 c 5 on-state drain current b i d(on) v ds 5 v, v gs = 5 v 10 a drain-source on-state resistance b r ds(on) v gs = 4.5 v, i d = 4.6 a 0.022 0.033 v gs = 3.0 v, i d = 4.3 a 0.025 0.038 v gs = 2.5 v, i d = 4.1 a 0.029 0.042 forward transconductance b g fs v ds = 10 v, i d = 4.6 a 25 s diode forward voltage b v sd i s = 1.2 a, v gs = 0 v 0.7 1.1 v dynamic a total gate charge q g v ds = 10 v, v gs = 4.5 v, i d = 4.6 a 6.5 10 nc gate-source charge q gs 1.2 gate-drain charge q gd 1.5 tu r n - o n d e l ay t i m e t d(on) v dd = 10 v, r l = 10 i d ? 1 a, v gen = 4.5 v, r g = 6 0.95 1.5 s rise time t r 1.4 2.1 turn-off delay time t d(off) 711 fall time t f 3.1 5 gate-current vs. gate-source voltage 0.000 0.005 0.010 0.015 0.020 0 3 6 9 12 15 - gate current (ma) i gss v gs - gate-to-source voltage (v) gate current vs. gate-source voltage 14 0.001 100 10,000 04 t j = 25 c - gate current (a) i gss 0.01 0.1 1 10 1,000 v gs - gate-to-source voltage (v) t j = 150 c 2681012
www.vishay.com 4 document number: 72215 s-81056-rev. b, 12-may-08 vishay siliconix si6924aedq typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current on-resistance vs. junction temperature 0 5 10 15 20 25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 v gs = 5 thru 2,5 v 2 v v ds - drain-to-source voltage (v) - drain current (a) i d 0.00 0.01 0.02 0.03 0.04 0.05 04812162 0 v gs = 4.5 v v gs = 2.5 v - on-resistance ( ) r ds(on) i d - drain current (a) v gs = 3 v 0.6 0.8 1.0 1.2 1.4 1.6 1.8 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 4.6 a t j - junction temperature (c) (normalized) - on-resistance r ds(on) transfer characteristics gate charge source-drain diode forward voltage 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 25 c t c = 125 c - 55 c v gs - gate-to-source voltage (v) - drain current (a) i d 0 1 2 3 4 5 01234567 v ds = 10 v i d = 4.6 a - gate-to-source voltage (v) q g - total gate charge (nc) v gs 1.0 1.2 1 10 20 0 0.4 0.6 0.8 t j = 25 c t j = 150 c v sd - source-to-drain voltage (v) - source current (a) i s
document number: 72215 s-81056-rev. b, 12-may-08 www.vishay.com 5 vishay siliconix si6924aedq typical characteristics 25 c, unless otherwise noted on-resistance vs. gate-to-source voltage single pulse power i d = 4.6 a - on-resistance ( ) r ds(on) v - gate-to-source voltage (v) 0.00 0.02 0.04 0.06 0.08 0.10 01234 5 i d = 4.6 a v gs - gate-to-source voltage (v) 0.001 0 1 50 60 10 30 10 0.01 power (w) time (s) 20 40 0.1 threshold voltage safe operating area - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a variance (v) v gs(th) t j - temperature (c) 100 1 0.1 1 10 100 0.01 10 1 ms - drain current (a) i d 0.1 limited by r * ds(on) t c = 25 c single pulse 10 ms 100 ms dc 10 s 1 s v ds - drain-to-source voltage (v) *v gs > minimum v gs at which r ds(on) is specified normalized thermal transient impedance, junction-to-ambient 2 1 0.1 0.01 10 -4 10 -3 10 -2 10 -1 1 100 600 duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse 1. duty cycle, d = 2. per unit base = r thja = 96 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm square wave pulse duration (s) normalized effective transient thermal impedance 10
www.vishay.com 6 document number: 72215 s-81056-rev. b, 12-may-08 vishay siliconix si6924aedq typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72215 . normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 110 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance
e1 e c r 0.10 (4 corners) b r 0.10 corners) a a2 a1 d l l1 k1 0.25 (gage plane) e package information vishay siliconix document number: 71201 06-jul-01 www.vishay.com 1
jedec part number: mo-153

dim min nom max a ? ? 1.20 a 1 0.05 0.10 0.15 a 2 0.80 1.00 1.05 b 0.19 0.28 0.30 c ? 0.127 ? d 2.90 3.00 3.10 e 6.20 6.40 6.60 e 1 4.30 4.40 4.50 e ? 0.65 ? l 0.45 0.60 0.75 l 1 0.90 1.00 1.10 y ? ? 0.10 k1 0 3 6 ecn: s-03946?rev. g, 09-jul-01 dwg: 5844
an1001 vishay siliconix document number: 70571 12-dec-03 www.vishay.com 1 little foot tssop-8 the next step in surface-mount power mosfets wharton mcdaniel and david oldham when vishay siliconix introduced its little foot mosfets, it was the first time that power mosfets had been offered in a true surface-mount package, the soic. little foot immediately found a home in new small form factor disk drives, computers, and cellular phones. the new little foot tssop-8 power mosfets are the natural evolutionary response to the continuing demands of many markets for smaller and smaller packages. little foot tssop-8 mosfets have a smaller footprint and a lower profile than little foot soics, while maintaining low r ds(on) and high thermal performance. vishay siliconix has accomplished this by putting one or two high-density mosfet die in a standard 8-pin tssop package mounted on a custom leadframe. the tssop-8 package little foot tssop-8 power mosfets require approximately half the pc board area of an equivalent little foot device (figure 1). in addition to the reduction in board area, the package height has been reduced to 1.1 mm. top view side view figure 1. an tssop-8 package next to a soic-8 package with views from both top and side this is the low profile demanded by applications such as pcmcia cards. it reduces the power package to the same height as many resistors and capacitors in 0805 and 0605 sizes. it also allows placement on the ?passive? side of the pc board. the standard pinouts of the little foot tssop-8 packages have been changed from the standard established by little foot. this change minimizes the contribution of interconnection resistance to r ds(on) and maximizes the transfer of heat out of the package. figure 2 shows the pinouts for a single-die tssop. notice that both sides of the package have source and drain connections, whereas little foot has the source and gate connections on one side of the package, and the drain connections are on the opposite side. figure 2. pinouts for single die tssop drain source source gate source source drain drain figure 3 shows the standard pinouts for a dual-die tssop-8. in this case, the connections for each individual mosfet occupy one side. figure 3. pinouts for dual-die tssop drain 1 source 1 source 1 gate 1 source 2 source 2 drain 2 gate 2
an1001 vishay siliconix www.vishay.com 2 document number: 70571 12-dec-03 because the tssop has a fine pitch foot print, the pad layout is somewhat more demanding than the layout of the soic. careful attention must be paid to silkscreen-to-pad and soldermask-to-pad clearances. also, fiduciary marks may be required. the design and spacing of the pads must be dealt with carefully. the pads must be sized to hold enough solder paste to form a good joint, but should not be so large or so placed as to extend under the body, increasing the potential for solder bridging. the pad pattern should allow for typical pick and place errors of 0.25 mm. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ), for the recommended pad pattern for pc board layout. thermal issues little foot tssop mosfets have been given thermal ratings using the same methods used for little foot. the maximum thermal resistance junction-to-ambient is 83 c/w for the single die and 125 c/w for dual-die parts. tssop relies on a leadframe similar to little foot to remove heat from the package. the single- and dual-die leadframes are shown in figure 4. figure 4. leadframe b) 8-pin dual-pad tssop a) 8-pin single-pad tssop the mosfets are characterized using a single pulse power test. for this test the device mounted on a one-square-inch piece of copper clad fr-4 pc board, such as those shown in figure 5. the single pulse power test determines the maximum amount of power the part can handle for a given pulse width and defines the thermal resistance junction-to-ambient. the test is run for pulse widths ranging from approximately 10 ms to 100 seconds. the thermal resistance at 30 seconds is the rated thermal resistance for the part. this rating was chosen to allow comparison of packages and leadframes. at longer pulse widths, the pc board thermal charateristics become dominant, making all parts look the same. figure 5. the actual test is based on dissipating a known amount of power in the device for a known period of time so the junction temperature is raised to 150 c. the starting and ending junction temperatures are determined by measuring the forward drop of the body diode. the thermal resistance for that pulse width is defined by the temperature rise of the junction above ambient and the power of the pulse, tja/p. figure 6 shows the single pulse power curve of the si6436dq laid o ver the curve of the si9936dy to give a comparison of the thermal performance. the die in the two devices have equivalent die areas, making this a comparison of the packaging. this comparison shows that the tssop package performs as well as the soic out to 150 ms, with long-term performance being 0.5 w less. although the thermal performance is less, little foot tssop will operate in a large percentage of applications that are currently being served by little foot. 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0.1 1 10 100 power (w) time (sec.) si6436 si9936 figure 6. comparison of thermal performance conclusion tssop power mosfets provide a significant reduction in pc board footprint and package height, allowing reduction in board size and application where soics will not fit. this is accomplished using a standard ic package and a custom leadframe, combining small size with good power handling capability. for the tssop-8 package outline visit: http://www.vishay.com/doc?71201 for the soic-8 package outline visit: http://www.vishay.com/doc?71192
an806 vishay siliconix document number: 70738 17-dec-03 www.vishay.com 1 mounting little foot tssop-8 power mosfets wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet, ( http://www.vishay.com/doc?72286 ), for the basis of the pad design for a little foot tssop-8 power mosfet package footprint. in converting the footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the tssop-8 package, the thermal connections are very simple. pins 1, 5, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in the dual package, pins 1 and 8 are the two drains. for a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. since the drain pins also provide the thermal connection to the package, this level of connection is inadequate. the total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. also, heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources when looking at heat spread on the pc board. figure 1. single mosfet tssop-8 pad pattern with copper spreading 0.032 0.8 0.018 0.45 0.284 7.6 0.073 1.78 0.118 3.54 0.026 0.66 0.122 3.1 the pad patterns with copper spreading for the single-mosfet tssop-8 (figure 1) and dual -mosfet tssop-8 (figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. to create this pattern, a plane of copper overlies the drain pins. the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and st art the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area under neath the body for this purpose. figure 2. dual mosfet tssop-8 pad pattern with copper spreading 0.026 0.66 0.284 7.6 0.032 0.8 0.122 3.1 0.091 1.65 0.073 1.78 0.018 0.45 since surface-mounted packages are small, and reflow soldering is the most common way in whic h these are affixed to the pc board, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.
application note 826 vishay siliconix document number: 72611 www.vishay.com revision: 21-jan-08 27 application note recommended minimum pads for tssop-8 0.262 (6.655) recommended mi nimum pads dimensions in inches/(mm) 0.092 (2.337) 0.182 (4.623) 0.040 (1.016) 0.026 (0.660) 0.014 (0.356) 0.012 (0.305) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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